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[VHDL-FPGA-Verilog] watch

Description: 用VHDL设计实现秒表功能：秒表功能包括开始/暂停键和清零键，精度要达到0.01秒，所以计数显示共有八个数码管，而每个数码管又有八个管脚，因此采用扫描显示的方法，减少管脚数量。时钟脉冲由最低位给入，采用异步方式驱动更高位的计数，时钟频率应该为100Hz，通过数码管显示，共有八个数码管，所以扫描频率应在100Hz的8倍以上。（付按键消抖代码）-VHDL design with a stopwatch functions: stopwatch features include Start/PAUSE button and the Clear, 0.01 seconds to achieve accuracy, so count showed a total of eight digital tube, each of the digital control and eight-pin, so the use of scan ways to reduce the number of pins. Clock pulse from the lowest to the income, the use of asynchronous drive higher bit count, the clock frequency should be 100Hz, digital display, a total of eight digital tube, the scanning frequency should be 8 times higher than 100Hz. (Pay button Buffeting code elimination)
Platform: | Size: 27648 | Author: 李月 | Hits:

[VHDL-FPGA-Verilog] sfsdfdsf

Description: 基于EDA的秒表的VHDL源代码，计数时间高达24小时。-VHDL-based EDA source code of a stopwatch, counting time up to 24 hours.
Platform: | Size: 156672 | Author: 千语千舒 | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: VHDL语言实现秒表并在共阴数码管上动态显示十进制数值-VHDL language stopwatch and digital control on a total of negative dynamic display decimal values
Platform: | Size: 53248 | Author: 高天天 | Hits:

[VHDL-FPGA-Verilog] MB

Description: vhdl秒表程序,从书上看到的例子，试了可以，值得学习。-vhdl stopwatch program, from the book to see examples of the test can be, it is worth learning.
Platform: | Size: 273408 | Author: 张双洋 | Hits:

[VHDL-FPGA-Verilog] SHUZIZHONGVHDL

Description: 多功能数字钟的VHDL编程实现，有与其他数字钟不同的秒表，闹钟等更多功能-Multi-function digital clock of VHDL programming, digital clock with other different stopwatch, alarm clock function, such as more
Platform: | Size: 29696 | Author: 赵彪 | Hits:

[VHDL-FPGA-Verilog] daima

Description: 用VHDL语言设计一个数字秒表： 1、 秒表的计时范围是0秒~59分59.99秒，显示的最长时间为59分59秒。 2、 计时精度为10MS。 3、 复位开关可以随时使用，按下一次复位开关，计时器清零。 4、 具有开始/停止功能，按一下开关，计时器开始计时，再按一下，停止计时。系统设计分为几大部分，包括控制模块、时基分频模块、计时模块和显示模块等。其中，计时模块有分为六进制和十进制计时器。计时是对标准时钟脉冲计数。计数器由四个十进制计数器和两个六进制计数器构成，其中毫秒位、十毫秒位、秒位和分位用十进制计数器，十秒位和十分位用六进制计数器。计时显示电路时将计时值在LED上七段数码管上显示出来。计时电路产生的计时值经过BCD七段码后，驱动LED数码管。-With VHDL language design digit stopwatch: 1, Stopwatch s time scope is 0 second ~59 minute 59.99 second, the demonstration longest time is 59 minute 59 second. 2, The time precision is 10MS. 3, The reset switch may momentarily use, presses down a reset switch, the timer reset. 4, Has starts/the stop function, according to the switch, the timer starts to time, presses again, stops timing. The system design divides into several major parts, including control module, time base frequency division module, time module and display module and so on. And, the time module influentials for the senary and the decimal base timer. The time is to the standard clock pulse counting. Counter by four decade counters and two senary counter constitution, a millisecond position, ten milliseconds positions, a second position and the rank with the decade counter, ten second position and ten ranks use the senary counter. When time display circuit will time the value on the nixietube to demonstrate on LED. The
Platform: | Size: 5120 | Author: SAM | Hits:

[VHDL-FPGA-Verilog] stopwatchVHDL

Description: Stopwatch program in VHDL using Xilinx.
Platform: | Size: 183296 | Author: dhiraj | Hits:

[VHDL-FPGA-Verilog] My_Clock

Description: 发个我的第一个VHDL代码，秒表。可暂停继续.清0。-My first one made a VHDL code, and a stopwatch. Continue to be suspended. Qing 0.
Platform: | Size: 585728 | Author: jemofh | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: VHDL语言实现的秒表设计，具有分秒，计数清零等功能-VHDL language implementation of the stopwatch design, with the minutes and seconds, counting functions such as Clear
Platform: | Size: 316416 | Author: tangchengjiang | Hits:

[Software Engineering] Design_of_multi-functional_sports_stopwatch

Description: 设计一个可以顺计时和倒计时的秒表。要求计时的范围为00.0S~99.9S，用三位数码管显示。用VHDL语言-Designed to be a cis-timing and countdown stopwatch. Required time ranges from 00.0S ~ 99.9S, with three digital tube display.
Platform: | Size: 234496 | Author: 林文 | Hits:

[VHDL-FPGA-Verilog] mb

Description: 简单秒表(1分钟)，希望对初学者有帮助，VHDL-Simple stopwatch (1 minute), want to be helpful for beginners, VHDL
Platform: | Size: 1046528 | Author: 陈俊 | Hits:

[VHDL-FPGA-Verilog] VHDLscounter

Description: 通过VHDL自行设计的一个秒表共有4个输出显示，分别为、十分之一秒、秒、十秒、分，所以共有4个计数器与之相对应（3个十进制计数器，一个6进制计数器用来对十秒进行计数），整个秒表还需有一个复位信号和一个精确的10HZ时钟信号。-Of a self-designed by VHDL stopwatch showed a total of four outputs, namely, one-tenth of seconds, seconds, ten seconds, minutes, so a total of four counters corresponding to (3 decimal counter, a 6 decimal counter is used to count for 10 seconds), the stopwatch should also have a reset signal and an accurate 10HZ clock signal.
Platform: | Size: 330752 | Author: zhangmin | Hits:

[VHDL-FPGA-Verilog] startwatch1

Description: 利用VHDL硬件描述语言实现 一个秒表设计，其中有5个VHDL文件。startwatch为顶层文件-The use of VHDL hardware description language designed to achieve a stopwatch, of which five VHDL files. startwatch for the top-level files
Platform: | Size: 3072 | Author: 李磊 | Hits:

[VHDL-FPGA-Verilog] CANDY1

Description: 用VHDL实现的数字钟，实现消抖，计时，显示分秒，秒表等功能-VHDL implementation with digital clock and realize elimination shake, timing, displays minutes and seconds, stopwatch functions
Platform: | Size: 1024 | Author: 凌云 | Hits:

[Other] VHDLforclock

Description: 用VHDL编写电子时钟芯片，具有整点报时，闹钟，秒表功能，调时可按十分与个位分别调时-The preparation of electronic clock chip with VHDL, with the whole point timekeeping, alarm clock, stopwatch function, can be transferred when the transfer is with a bit difference when the
Platform: | Size: 4539392 | Author: 林寒 | Hits:

[VHDL-FPGA-Verilog] electricwatch

Description: 用VHDL语言设计多功能的电子表。实现基本电子表的时间显示、闹钟、秒表等功能-VHDL language design with multi-functional electronic watch. The time table to achieve basic electronic display, alarm clock, stopwatch functions
Platform: | Size: 974848 | Author: mollyma | Hits:

[OS program] b

Description: 基于VHDL的数字时钟设计与实现。。。。可以实现时钟，秒表-VHDL-based Design and Implementation of Digital clock. . . . Can achieve clock, stopwatch. .
Platform: | Size: 720896 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] biao

Description: 用VHDL 描述的 “秒表"程序设计-Described using VHDL programming stopwatch
Platform: | Size: 1024 | Author: chong | Hits:

[VHDL-FPGA-Verilog] 5

Description: 基于FPGA的数字秒表的VHDL设计,论文,有主要程序-FPGA-based VHDL design digital stopwatch, paper, a major program
Platform: | Size: 1024 | Author: 孤星寒 | Hits:

[VHDL-FPGA-Verilog] 3

Description: 】文章介绍了用于体育比赛的数字秒表的VHDL 设计, 并基于FPGA 在MAXPLUS2 软件下, 采用ALTRA 公司FLEX10K 系列的EPF10K10LC84- 4 芯片进行了计算机仿真-】 This article introduces digital stopwatch for sports competition in the VHDL design and FPGA-based software in MAXPLUS2, using ALTRA company FLEX10K series EPF10K10LC84-4 chip, the computer simulation
Platform: | Size: 50176 | Author: 孤星寒 | Hits:
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